To meet demands for faster processors and higher capacity memories, integrated circuit (IC) designers are focusing on decreasing the minimum feature size within ICs. By minimizing the feature size within an IC, device density on an individual chip increases exponentially, as desired, enabling designers to meet the demands imposed on them. As the minimum feature size in semiconductor ICs decreases, however, capacitive coupling between adjacent conductive layers is becoming problematic. In particular, for example, capacitive coupling between metal lines in the metallization level of ICs limits the minimum feature size that is operatively achievable.
One attempt to minimize the problem of capacitive coupling between metal lines involves utilizing a relatively low dielectric constant material to insulate the metal lines. Conventionally, silicon dioxide (SiO.sub.2), having a dielectric constant of about 4.0.epsilon..sub.0 (wherein .epsilon..sub.0 is the permittivity of space), is used as the insulating material in ICs. To date, the minimum dielectric constant possible, however, is that of air, the dielectric constant being 1.0.epsilon..sub.0. Nevertheless, the use of air as an insulating material, such as provided using an air bridge, has drawbacks. For example, IC structures utilizing air insulation lack mechanical strength and protection from their environment.
SiO.sub.2 and air have been utilized together in an inorganic, porous silica xerogel film in order to incorporate both the mechanical strength of SiO.sub.2 and the low dielectric constant of air. In this manner, SiO.sub.2 behaves as a matrix for porous structures containing air. However, porous silica xerogel film has a tendency to absorb water during processing. The water absorbed during processing is released during aging, resulting in cracking and a pulling away of the porous silica xerogel film from the substrate on which it is applied.
Even when nonporous SiO.sub.2 is utilized, as the minimum feature size within an IC decreases, significant stress develops at the interface between the SiO.sub.2 and metal on which SiO.sub.2 is commonly formed, causing potentially detrimental disruptions in the electrical performance of the IC. For example, the stress may be great enough to rupture a metal line adjacent to the SiO.sub.2 insulating layer. Such stress develops from the large difference in the coefficient of thermal expansion between that of SiO.sub.2 and that of the metal. The coefficient of thermal expansion of SiO.sub.2 is about 0.5 .mu.m/m.degree. C. to about 3.0 .mu.m/m.degree. C. The coefficient of thermal expansion of Type 295.0 aluminum, an alloy similar in composition to the aluminum alloys commonly used in the metallization level of an IC, is about 23 .mu.m/m.degree. C. The coefficient of thermal expansion for aluminum is significantly higher than that of SiO.sub.2. Likewise, the coefficient of thermal expansion of Type C81100 copper, an alloy similar in composition to a copper alloy which may also be used in integrated circuit metallization layers, is about 16.9 .mu.m/m.degree. C., also significantly higher than that of SiO.sub.2. The metallization layer's larger coefficient of thermal expansion results in its absorption of all of the strain caused by the large difference in the coefficients of thermal expansion upon heating and cooling. The result of such strain absorption is that the metallization layer is placed in tension and the SiO.sub.2 layer is placed under slight compression. The high compressive yield strength of SiO.sub.2 prevents its rupture. In contrast, the relatively low tensile yield strength of the metallization layer promotes its rupture, leading to integrated circuit failure.
It has also been reported that certain polymeric materials have dielectric constants less than that of SiO.sub.2. For example, polyimides are known to have a dielectric constant of about 2.8.epsilon..sub.0 to about 3.5.epsilon..sub.0. The use of polyimides in the metallization level of ICs is well known. For example, Carey (U.S. Pat. No. 5,173,442) reported the use of a polyimide as an interlayer dielectric.
Others have reported that foaming (i.e., introducing air into) polymeric material results in a material having a dielectric constant of about 1.2.epsilon..sub.0 to about 1.8.epsilon..sub.0. One such foaming process is described by Cha et al. (U.S. Pat. No. 5,158,986). The exact dielectric constant of such foamed polymers depends on the percentage of voids (i.e., air) present and the dielectric constant of the polymeric material that was foamed. The use of such foamed polymers, however, has been limited to electronic packaging applications and multichip module applications for microwave substrates. Multichip module processing is not suitable for use in semiconductor fabrication because in multichip module processing, a metal insulator "sandwich" is formed as a unit and is then applied to a surface. Due to the oftentimes uneven topographies at the metallization level of an IC, each of the metal layer and the insulation layer need to be formed separately, allowing them to conform to the underlying topography.
Therefore, there is a need for an insulating material for use in an integrated circuit that has adequate mechanical integrity, as well as a relatively low dielectric constant. The capacitive coupling problem between conductive layers needs to be minimized as device density continues to increase within an integrated circuit.